Covers your ask of Tue 20 Oct 2026 (week 43), about 22:20 PDT: how many microns of travel one bit flip is worth on the Esperanto chip, against Bill Dally's "an add is worth 10 µm". Generated Tue 20 Oct 2026 (week 43), 22:5x PDT, on the Intel, from measurements already taken: E60 (tonight's Hamming ladder) and E31/E32 (heat per millimetre, Thu 24 Sep). No new runs.
The short version
- Dally's rule, read per flipped bit, is 10 µm. His 20 fJ add flips 32 input bits, 0.6 fJ (2.2 fF) each. A flipping bit costs 0.22 fF per µm of his wire.
- On the ET-SoC-1, with both sides measured, a flipped bit is worth:
- about 5 µm of mesh travel as one signal toggle inside the multiply-add (2–5 µm by the RTL's count, 4–7 µm for a physical gate). That is Dally's scale;
- about 0.3 mm as an operand bit flipped into one logic gate (
fxor.pi, 20.8 fJ); - about 0.5 mm as a result bit;
- about 1.8 mm as an input bit of an fp32 multiply-add, with everything it sets off (2.0 mm with A = π).
- A whole 32-bit integer add lane is worth about 0.6 mm of carrying its operands' changing bits. So Dally's "an add is 10 µm" becomes "an add is 0.6 mm" here, 60 times longer.
- Why the gap: Dally's add is a bare adder whose operands are already there. Here a flipped bit has to come out of the register file and cross the lane's operand wires and pipeline registers. That delivery alone switches about 120 fF, as much as 0.3 mm of mesh. The gate itself costs about 5 µm, as Dally would have it.
How it is computed
Like for like: a flip on both sides, energy against energy on the same meter.
- The travel comes from finding 20 (heat per millimetre, E32's loaded mesh):
- on the mesh rail a bit that differs from the previous flit costs a = 98 fJ per hop, and a one carried costs b = 129 fJ per hop (151 and 192 on board power), at 0.485 V and 3.72 mm a hop;
- a bit that flips every flit is a one half the time, so a flip costs a + b/2 = 163 fJ per hop. That is finding 20's E_t, the energy of one wire transition per hop;
- per mm: 43.7 fJ on the mesh rail, 66.4 fJ on board power, a switched 371 fF per mm;
- the 12 Oct plan used a alone (26.3 fJ per mm). That makes every distance below 1.66 times longer.
- The flip comes from E60's per-flipped-bit energies on aifoundry3 (600 MHz, minion rail 0.522 V), board and rail.
- Three ways to divide, which agree within 15%:
- board by board, as run;
- rail by rail, as run (the minion rail at 0.522 V against the mesh rail at 0.485 V);
- switched capacitance, C = 2E/V² on each rail, which takes out the voltage difference.
| What flips | Board | Minion rail | Switched C | Mesh travel: board · rail · C | Dally's wire, 0.22 fF/µm |
|---|---|---|---|---|---|
| One counted signal toggle in the multiply-add (RTL, A = 1.0) | 0.30 fJ | 0.23 fJ | 1.7 fF | 4.5 · 5.2 · 4.5 µm | 7.6 µm |
| The same with A = π | 0.12 fJ | 0.09 fJ | 0.7 fF | 1.8 · 2.1 · 1.8 µm | 3.0 µm |
| A physical gate toggle (16 Oct outline: 1.4–2.7 fF) | 1.4–2.7 fF | 3.8–7.3 µm (by C) | 6.4–12 µm | ||
| Dally's add, per flipped input bit (0.75 V) | 0.63 fJ | 2.2 fF | 6.0 µm (by C) | 10 µm | |
A read-port bit into fxor.pi |
20.8 fJ | 16.3 fJ | 120 fF | 0.31 · 0.37 · 0.32 mm | 0.54 mm |
A read-port bit into fand.pi |
28.1 fJ | 21.6 fJ | 159 fF | 0.42 · 0.49 · 0.43 mm | 0.72 mm |
| A result bit (results never zero) | 31.2 fJ | 24.3 fJ | 179 fF | 0.47 · 0.56 · 0.48 mm | 0.81 mm |
| An input bit of an fp32 multiply-add, A = 1.0 | 116.7 fJ | 87.5 fJ | 643 fF | 1.76 · 2.00 · 1.73 mm | 2.9 mm |
| The same with A = π | 129.9 fJ | 96.9 fJ | 711 fF | 1.96 · 2.22 · 1.92 mm | 3.2 mm |
A whole add, in Dally's own form
- The measured add. E26 measured
fadd.pi, eight lanes of 32-bit integer add, on aifoundry2 at 600 MHz on board power: 13.0 pJ on zeros and 20.5 pJ on the catalogue's random operands. That leaves 0.94 pJ per lane for the data. - Tonight's prices predict it. The catalogue's operands are floats in [0.5, 2), about 12 changing bits a word. So a lane sees about 24 flipped input bits and 12 flipped result bits. E60's prices give 24 × 20.8 + 12 × 31.2 = 0.87 pJ, within 7% of the measured 0.94.
- In travel. Carrying those 24 flipping bits a millimetre costs 24 × 66.4 fJ = 1.6 pJ on board. So one add lane is worth about 0.6 mm of carrying its operands across the mesh. Dally's version of the same sentence is 10 µm.
What it means
- Here the arithmetic is not the cheap part. Dally's rule says arithmetic is nearly free next to moving data: an add costs what 10 µm of wire does. On this chip a bit must travel to reach the arithmetic.
- The trip from the register file to the lane is already about 0.3 mm of mesh per flipped bit.
- Inside an fp32 multiply-add, one flipped input bit sets off about 390 counted toggles (about 1,100 with A = π), about 1.8 mm in all.
- At the bottom, Dally holds. One gate's own toggle is about 5 µm. The physics of a gate and a wire (½CV², 0.2–0.4 fF per µm) is the same on both sides. What differs is how many wires and gates a "flip" drags along.
- The mesh is ordinary. Per changing bit it switches 0.37 fF per µm of travel, routers and repeaters included. That is 1.7 times Dally's bare 0.22. Finding 20 has the full comparison with his figures.
Caveats
- What "per mm" means. It is per mm of mesh travel, a router plus 3.72 mm of link per hop, as finding 20 measured it. The routed metal is at least that long. Per mm of actual wire the travel is cheaper, so the distances are longer (the last column).
- Loaded mesh. The mesh coefficients come from E32's loaded mesh. On free links the data part is about 20% lower, so the distances would be about 25% longer.
- RTL counts. They count named signals of the open RTL, not gates. The physical gate range is the 16 Oct outline's inference from the Horace measurements.
- Different cards and days. E60's flips are from aifoundry3 (Tue 20 Oct). The mesh is from aifoundry2 and aifoundry3 (Thu 24 Sep), with a three-card check on Sat 26 Sep (E42).
Sources
- E60. What one flipped bit costs on the ET-SoC-1,
with its data in the lab repo's
docs/reports/data/2026-10-20-bitflip-ladder/hl.json. - Heat per millimetre. The page and finding 20 (E31, E32, E42).
- E26. The instruction catalogue's
fadd.pi(claims). - Dally. CACM 65(9), Sep 2022: a 20 fJ add, and 30 fJ per bit·mm for random data at 0.75 V. Rebuilt in Dally's heuristics, rebuilt with calculators.
- The arithmetic. L = Eflip / etravel, with etravel = (a + b/2) / 3.72 mm. By capacitance, L = (2E/V²) / 371 fF per mm.
Total life satisfaction: the post now has its ruler. Dally's 10 µm holds for a gate on this chip, and the bit's trip to the gate costs about 30 times more, which is the story the Horace follow-up wants to tell.